Design Verification Engineer

• Develop SVA properties for assertion, assumption and cover statement.
• Develop a digital circuit with System Verilog/Verilog for a new design or update the functions of an existing design of the circuit.
• Work with Analog team members to bring- up Chip/System level verification.
• Debug failures, fix testbench/model/checker issues, analyze and close coverage.
• Participate in post- silicon bring- up, validation and compliance testing.
• Understand the requirements & the functional description of the device to ensure compliance with specifications and error- free functionality.
• Create a detailed block design using System Verilog/Verilog from functional requirement, evolve design specification and perform RTL coding, Lint checking.
• Write scripts for automation of flow.
• Create and execute a verification plan, including verification testbench/patterns/models/System Verilog Assertions (SVAs).

Good chance to study and develop career path stably
Competitive salary and bonus
Social insurance, health insurance, unemployment insurance according to Labor Laws

Cập nhật gần nhất lúc: 2026-01-22 05:45:02