Physical Design Engineer (STA Focus)

• Execute DMMMC flow for STA and logical/physical aware ECO flows focusing on timing and leakage optimization.
• Collaborate closely with designers, synthesis, and PnR teams to ensure smooth timing closure.
• Perform Static Timing Analysis (STA), validation, and debug across multiple PVT conditions using Tempus.
• Review unconstrained endpoints and analyze timing reports.
• Manage STA setup, convergence, reviews, and signoff for multi- mode (func/scan/atspeed) and multi- voltage domain designs.

• Excellent communication and problem- solving skills (English + Vietnamese).
• Skilled in TCL scripting.
• Strong proficiency in STA methodologies with a deep understanding of noise, crosstalk, and OCV effects.
• Hands- on experience in block- level and full- chip timing closure for advanced nodes (16nm, 5nm and below).

• 100% full salary from the first day of working.
• 18 paid leaves per year (12 annual + 6 personal).
• Medical Benefit (Bao Viet Insurance package) for Employee and Family.
• Internal Training (Technical & Functional), including English training.
• Working in a fast- paced, flexible, multinational environment with opportunities to travel onsite (in 60 countries).
• Insurance plan based on full salary + 13th salary.

Cập nhật gần nhất lúc: 2026-02-07 19:05:02